Functional Vector Generation for HDL models Using

| Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model describes interconnections of arithmetic, logic and memory modules. Given a path in the HDL model, the search for input stimuli that exercise the path can be converted into a standard satissability checking problem by expanding the arithmetic modules into logic-gates. However, this approach is not very eecient. We present a new HDL-satissability checking algorithm that works directly on the HDL model. The primary feature of our algorithm is a seamless integration of linear-programming techniques for feasibility checking of arithmetic equations that govern the behavior of data-path modules, and satissability checking for logic equations that govern the behavior of control modules. This feature is critically important to eeciency, since it avoids module expansion and allows us to work with logic and arithmetic equations whose cardinality tracks the size of the HDL model. We describe the details of the HDL-satissability checking algorithm in this paper. Experimental results which show signiicant speedups over state-of-the-art gate-level satissability checking methods are included.